1. Field of the Invention
The present invention relates to a process for manufacturing a non volatile memory, particularly a memory of the EPROM, EEPROM or Flash EEPROM type with a double layer of polycrystalline silicon, in standard or AMG (Alternate Metal Ground) configuration. More particularly, the invention relates to a process that reduces the resistance of the common source lines in the matrix of memory cells.
2. Discussion of the Related Art
In matrixes of self-aligned cells, present in EEPROM, EPROM and Flash EEPROM non-volatile memories with double layer of polycrystalline silicon, in standard or AMG configuration, the common source lines have, at the end of the manufacturing process, deep silicon excavations (for instance of depth equal to 2500 .ANG.) in particular zones of active area, more precisely in the zones where the lower polysilicon layer is etched and removed during the step of isolation of the floating gates of the memory cells belonging to a same row ("word line") of the matrix.
In fact, during a conventional manufacturing process for a matrix of non-volatile memory cells, for instance of the EEPROM type, after having defined the zones of active area, covered by a thin layer of oxide (gate oxide), and the zones of field oxide, a first layer of polycrystalline silicon or polysilicon is deposited on the whole surface of the wafer and then, through a suitable mask, the first polysilicon layer is etched to form regions of lower polysilicon along the active areas.
During the aforesaid phase of etching the first polysilicon layer, zones of active area are created that are no longer covered by the first polysilicon layer: these zones will be those in which the aforesaid deep excavations will subsequently be formed.
Once the aforesaid regions of lower polysilicon have been defined, an intermediate dielectric layer (for instance ONO) is grown on the whole surface of the wafer and then, through deposition of a second polysilicon layer and following selective etch, seconds strips of upper polysilicon, superimposed on and transverse to the aforesaid regions of lower polysilicon are defined, that constitute the word lines.
At this step, the intermediate dielectric is etched in self-aligned manner with the strips of upper polysilicon, and during this phase the gate oxide present on the zones of active area that are no longer covered by the lower polysilicon is also etched, leaving the underlying silicon uncovered.
In the following etching phase of the lower polysilicon, also this time self-aligned with the intermediate dielectric and the upper polysilicon, for the definition of the self-aligned cells, the aforesaid zones of active area, no longer covered by the lower polysilicon or by gate oxide, are etched and therefore excavations in the uncovered silicon are formed.
The presence of these excavations results in, during the following LDD etch, the formation of narrow spacers of oxide on the walls of the same excavations, of extremely varying width, that may screen, in an undesired way, the N+ implant of source and drain of the memory cells that follows.
In FIG. 1 there is for instance shown a cell 30 of a non-volatile memory matrix of the EEPROM type, and in the FIGS. 2 and 3 there are shown the cross-sections of the cell 30 along the lines II--II and III--III, respectively.
The memory cell 30 includes a floating gate transistor 31, a selection transistor 32, an N type drain region 4 with respective external contact 5 and a source region, included in an N type common source line 3. The floating gate transistor 31 includes, in turn, a floating gate 140 and a superimposed control gate 210, this last associated with a row or word line 1 of the matrix, and a layer of intermediate oxide 15 among the two aforesaid gates. The selection transistor 32 also includes two gates, respectively the gate 141 and the gate 211, superimposed and short-circuited externally to the matrix, and is associated with a selection line 2, parallel to the row 1 of the memory matrix. Among the floating gate transistor 31 and the selection transistor 32, along the active area, an N type region 8 is provided, while on the thin gate oxide layer (typically of thickness ranging between 150 and 300 .ANG.), underlying the floating gate 140, an even thinner portion of oxide 16 is present (tunnel oxide, typically of thickness ranging between 70 and 120 .ANG.), under which an N type region 6 is implanted, through a special mask 7, to allow the passage of the electrons for tunnel effect from the drain to the floating gate, and viceversa, when the information is stored in the memory cell.
In FIG. 1 are also visible (in dashed line) the windows of a photolithographic mask 9, used in the initial etch of a lower polysilicon layer 14 for the definition of the floating gates 140 and (in dash-and-dot line) a window of a photolithographic mask 7 used for the dopant implant under the tunnel oxide 16.
In FIG. 2 the section II--II of FIG. 1 is shown: on a P type substrate 11 a thin gate oxide layer 13 is present through which N type implants are performed for the source and drain regions 3, 4, as well as for the region 8 forming both the drain electrode of the floating gate transistor 31 and the source electrode of the selection transistor 32.
Also visible are the N type deep region 6 under the tunnel oxide 16, and an N type region 12, also deep, in correspondence to the external drain contact 5.
Both the floating gate transistor 31 and the selection transistor 32 are formed by a first polysilicon layer 14 (lower polysilicon), an intermediate dielectric layer 15 and a second polysilicon layer 21, on which a layer of salicide 17 can optionally be defined. Also visible are the spacers of oxide 18 on the walls of the gates.
FIG. 3 shows the cross-section III--III of FIG. 1, in which the two gates are present above a thick field oxide layer 19. Thanks to the mask 9, used in the initial etch of the lower polysilicon for the definition of the gates, the row 1 of the matrix results composed of only two layers, the upper polysilicon layer 21 and the salicide layer 17, and besides the region of common source 3 has an excavated zone 10 (in figure there is also shown in dot line the profile 20 of the source region 3 before that, during the etch that defines the words line, silicon is excavated). As in FIG. 2, the spacers 18 are visible, whose width can create problems of masking of the excavated regions 10 during the following N type implant for the formation of the drains and the sources, particularly of the common source lines 3.
The elimination or the reduction of the width of the spacers 18 on the walls of the excavations 10 are not feasible since their formation depends on the inherent misalignment in the lithographic process and on the natural variability of the LDD etch process.
Besides, in the most advanced process, the diffusions of source and drain are very thin and therefore in correspondence to the aforesaid excavations 10, where a considerable gradient is present, there is obtained a narrowing of the diffusion and consequently the resistance of the source line 3 can be very elevated (as well as varying from lot to lot due to the process variations). As can be noticed in FIG. 4, that shows the section IV--IV of FIG. 1 along the common source line 3, along the source line problems of connection between excavated regions 10 and non-excavated regions can be experienced.
In view of the state of the art described, the object of the present invention is that of providing a process of manufacturing that allows decreasing the resistance of the common source line of a matrix of self-aligned non-volatile memory cells.